Credo PCIe 6 retimers deliver 40dB reach and sub 7ns latency at 11W, allowing designers to extend their PCIe traces while ensuring best-in-class system performance.
HiWire AECs integrate retimer, gearbox, and forward error correction functionality into smaller gauge copper cables as an alternative to AOCs and DACs at 400G and beyond.
Our cutting-edge optical devices are renowned for high performance, low power, and cost optimization and offer a range of solutions for hyperscale data centers, AI, 5G, and telecom deployments.
Credo stands as a leader in SerDes IP for custom ASICs. Seamlessly integrate Credo's SerDes into next-generation ASICs with our advanced IP and Chiplet.
Credo retimers, gearboxes, and MACsec devices facilitate PAM4/NRZ line card and backplane connectivity at up to 112G per lane. They enable platforms with capabilities reaching 52.1Tbps, featuring 800G ports.
Credo Predictive Integrity Link Optimization and Telemetry (PILOT) is a powerful Software Development Kit (SDK) that enables rapid system bring-up, deep visibility into PCIe link behavior, and predictive insight into signal integrity issues—before they become system-level failures.
"We Connect," extends beyond data centers. It's integrated into our company culture and resonates in our engagement with local community programs.
Today Credo announced that Bill Brennan, Chairman, President and CEO, and Dan Fleming, CFO, are scheduled to present at the upcoming 2025 Goldman Sachs Communacopia + Technology Conference in San Francisco on Wednesday, September 10, 2025.
Credo's first quarter fiscal year 2026 financial results will be announced on September 3, 2025. Interested parties may join the conference call beginning at 2:00 pm Pacific Time.
